Microcontroller waveform generation

ABSTRACT

One embodiment of the present invention is a microcontroller ( 24 ) including an embedded memory ( 42 ), waveform control circuitry ( 44 ) operatively coupled to the memory ( 42 ), several terminals ( 52 ), and a programmable processor ( 30 ). Processor ( 30 ) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory ( 42 ) with a desired transmission timing. Waveform circuitry ( 44 ) is responsive to processor ( 30 ) to control transmission of the waveform bit pattern stored in memory ( 42 ) through one or more of the terminals ( 52 ) in accordance with the timing while processor ( 30 ) executes the second sequence of instructions to perform a different process.

The present invention relates to electronic devices, and moreparticularly, but not exclusively, relates to generation of waveformswith a microcontroller.

There is a frequent desire to generate sequential bit patterns withpredictable timing and/or frequency with a microcontroller.Unfortunately, generation of such desired patterns as a directconsequence of Central Processing Unit (CPU) instruction execution isoften impractical because of variation in CPU instruction timing, higherpriority CPU tasks, asynchronous interrupt servicing, and the like.Indeed, the operating system and other overhead tasks of manymicrocontroller applications often preclude direct sequential bitpattern generation with the CPU.

Thus, there is an ongoing demand for further contributions in this areaof technology.

One embodiment of the present invention is a unique electronic devicefor generating bit patterns. Other embodiments of the present inventioninclude unique devices, methods, systems, and apparatus to generatewaveforms with a microcontroller.

A further embodiment includes providing a microcontroller integratedcircuit that has a programmable processor, an embedded memoryoperatively coupled to the processor, waveform control circuitryoperatively coupled to the processor and the memory, and severalterminals for coupling to external circuitry. In accordance withprogramming executed by the processor, a waveform bit pattern is storedin the memory. The waveform circuitry controls synchronous transmissionof the waveform bit pattern stored in the memory through one or more ofthe terminals in accordance with designated timing. During thistransmission, an instruction sequence for a different process can beexecuted by the processor.

Still a further embodiment includes: providing a microcontrollerintegrated circuit having a programmable processor, an embedded memory,waveform control circuitry, and several input/output pins; executing afirst instruction sequence with the processor; initiating transmissionof a waveform bit pattern stored in the memory through one or more ofthe pins and controlling timing of the transmission; and executing asecond instruction sequence with the processor during this transmission.

Yet another embodiment is directed to an apparatus comprising: amicrocontroller integrated circuit device that includes an embeddedmemory, waveform control circuitry operatively coupled to the memory,several input/output pins, and a programmable processor. Theinput/output pins are each structured to be selectively switched betweenthe memory and at least one different embedded device. The processorincludes means for executing a first sequence of instructions to store awaveform bit pattern in the embedded memory and designate timing for thewaveform bit pattern. The waveform circuitry includes means forcontrolling synchronous transmission of the waveform bit pattern storedin the memory through one or more of the input/output pins in accordancewith the timing while the processor executes a second sequence ofinstructions to perform a different process.

One object of the present invention is to provide a unique electronicdevice for generating bit patterns.

Another object of the present invention is to provide a unique device,method, system, or apparatus to generate waveforms with amicrocontroller.

Further objects, embodiments, forms, features, benefits, and advantagesof the present invention shall become apparent from the description andfigures included herewith.

FIG. 1 is a diagrammatic view of a electronic device system.

FIG. 2 is a flowchart corresponding to operation of the system of FIG.1.

While the present invention may be embodied in many different forms, forthe purpose of promoting an understanding of the principles of theinvention, reference will now be made to the embodiments illustrated inthe drawings and specific language will be used to describe the same. Itwill nevertheless be understood that no limitation of the scope of theinvention is thereby intended. Any alterations and further modificationsin the described embodiments, and any further applications of theprinciples of the invention as described herein are contemplated aswould normally occur to one skilled in the art to which the inventionrelates.

One embodiment of the present invention is directed to a microcontrollerintegrated circuit including an embedded memory operatively coupled tothe processor, waveform control logic operatively coupled to the memory,and a programmable processor. This processor executes a first processthat includes storing a waveform bit pattern in the embedded memory withdesignated waveform transmission timing. Transmission of the waveformbit pattern from the memory through one or more terminals is performedunder control of the waveform logic. The processor executes a differentprocess as the transmission occurs.

FIG. 1 depicts another embodiment of the present invention in the formof electronic device system 20. System 20 includes microcontrollerintegrated circuit 22 that is of a solid state variety and may bemanufactured using standard photolithographic techniques.Microcontroller circuit 22 defines microcontroller 24 that includesembedded circuitry operable to perform various microcontrolleroperations. This circuitry includes processor 30, interrupt controllogic 32, input/output configuration registers 34, and other embeddeddevices 36. Processor 30 is of a programmable type that executes asequence of instructions of a Complex Instruction Set Computing (CISC)type, a Reduced Instruction Set Computing (RISC) type, or different typeas would occur to one skilled in the art. In one form, instructions arestored in memory coupled to processor 30 via a local bus. Such memorycan include Static Random Access Memory (SRAM) memory, nonvolatile flashmemory, Dynamic Random Access Memory (DRAM), and/or such different typeas would occur to those skilled in the art.

Interrupt control logic 32 manages internal and external interruptsassociated with microcontroller 24, and may be coupled to processor 30by an appropriate internal bus.

Devices 36 include any of various standard input devices, outputdevices, Input/Output (I/O) devices, and/or different dedicated circuitdevices. Devices 36 can include one or more timers, real-time clocks,analog-to-digital (A/D) converters, digital-to-analog (D/A) converters,Universal Asynchronous Receiver/Transmitter (UART) interfaces and/orvarious other serial communication ports, external interrupt pathways,pulse-width modulators, or the like, just to name a few. A high-speedinternal bus can be used to couple processor 30 and devices 36 togetherto provide selective bidirectional communication therebetween. In onevariation of this form, the bus is coupled to processor 30 via aninterface bridge (not shown). Philips Semiconductors model LPC2114 andmodel LPC2124 are nonlimiting examples of microcontroller configurationsthat include processors, interrupt control logic, I/O and variousdedicated embedded devices of a type that could be included inmicroprocessor circuit 22.

Microcontroller 24 further includes waveform generation circuitry 40.Circuitry 40 includes waveform bit pattern storage memory 42 andwaveform control logic circuitry 44 coupled to processor 30 by bus 38.Processor 30 has read/write access to memory 42. Memory 42 can be thesame or different than other memory coupled to processor 30 forprogramming and/or processor data storage, and bus 38 can be the same ordifferent than buses coupled to such processor memory, to interruptcontrol logic 32, to devices 36, or the like. Waveform logic 44 isoperatively coupled to memory 42 to provide control thereof withoutadding appreciable traffic along bus 38. Waveform logic 44 includes atleast one timer 46 that is synchronized to operation of processor 30 ina standard manner. For example, processor 30 and timer 46 can share acommon clock and/or different time-base circuitry (not shown). Waveformlogic 44 is responsive to input received from processor 30 via bus 38 tocontrol certain aspects of waveform generation based on the patterninformation stored in memory 42, as will be described in greater detailin connection with FIG. 2 hereinafter.

Microcontroller 24 also includes several shared input/output pins 48more specifically designated pins P0, P1, . . . , and PN; where thevariable “N” relates to the total N+1 number of pins. Each pin 48 isconnected to a pin-level logical selection block 50 designated PIN SEL0, PIN SEL 1, . . . , and PIN SEL N in FIG. 1, with the verticalellipsis of FIG. 1 representing pin P2 through pin PN-1, and block PINSEL 2 through block PIN SEL PN-1. Reference numerals 50 a, 50 b, and 50c are also provided referring more specifically to blocks PIN SEL 0, PINSEL 1, and PIN SEL N; respectively.

Blocks 50 are each configured to select from among memory 42 and “x”number of pathways from other devices 36, where x is an integer value ofat least one. Some, all, or none of the outputs of Block 42 may also beconnected directly to the input/output pins. Selection, or “switchingbetween” memory 42 and devices 36 is performed based on a selection bitinput value stored in and provided from one of registers 34, as loadedby processor 30. While the arrowhead directions represent outgoingsignals from other devices 36, it should be appreciated that one or moreof these may be inputs through pins 48 for certain embodiments, where atleast a portion of pins 48 are switchable between input and outputoperation. In one particular, nonlimiting embodiment, some or all ofpins 48 are of a general purpose input/output type. Likewise, in otherembodiments, some or all of pins 48 can be dedicated only to output.Alternatively or additionally, at least some of “x” number of pathwaysmay be associated with memory or other arrangements besides devices 36(not shown). Pins 48 correspond to terminals 52 of microcontrollercircuit 22 that are more specifically designated terminals 52 a, 52 b,and 52 c in correspondence to pins P0, P1, and PN. Pins 48 (terminals52) are arranged to be coupled to circuitry and/or signal pathwaysexternal to microcontroller integrated circuit 22.

External to microcontroller circuit 22, bus 60 is coupled to pins 48 andcircuit device 62. Bus 60 is also coupled to input data latch 70. Latch70 is embedded in microcontroller integrated circuit 22. It should beappreciated that latch 70 could be included among devices 36; however,it is shown separately in FIG. 1 to preserve clarity. Furthermore, theinput to latch 70 from bus 60 and/or device 62 can be provided viageneral purpose input/output pins or the like. Latch 70 also receivesinput from device 62. In one specific arrangement, device 62 includes amemory and bus 60 is utilized to strobe data into latch 70 from thisexternal memory.

FIG. 2 depicts one type of operating procedure 120 for system 20 inflowchart form; where like reference numerals refer to like featurespreviously described. Procedure 120 begins with operation 122. Inoperation 122, processor 30 executes programming, including a routinewith a sequence of instructions that directs generation of a desiredwaveform over bus 60 through one or more of pins 48 with a desiredtiming/frequency relationship. Rather than directly generate thiswaveform from instructions as they are executed by processor 30,waveform generation circuitry 40 is utilized. Specifically, the routineexecuted by processor 30 directs storage of data in memory 42 via bus38. This data provides a waveform bit pattern to be transmitted onto bus60. In one nonlimiting application, this waveform bit pattern isselected to appropriately strobe data into latch 70 from device 62.

From operation 122, procedure 120 continues with operation 124, whichfurther sets-up waveform generation. In operation 124, waveformgeneration set-up includes storage of selection data in one or more ofregisters 34 to select memory 42 with blocks 50 as an input source.Correspondingly, output from memory 42 through blocks 50 is provided tobus 60 via selected pins 48 (terminals 52). It should be appreciated,the selection blocks 50 can be used to vary the number of pins 48receiving input from memory 42 in operation 124. Alternatively, thisquantity can be fixed for a given embodiment.

From operation 124, operation 126 is performed. In operation 126,waveform logic 44 responds to input from processor 30 to initiatetransmission of the waveform bit pattern from memory 42 through pins 48.This input could include one or more commands directing a number ofaspects of the transmission, such as frequency or other transmissiontiming parameters. For example, the transmission could be specified as a“one time only” type or set to repeat. In one embodiment of therepeating type, microcontroller 24 can be arranged with a processorcommand structure recognized by waveform circuitry 44 that specifies afinite number of repetitions or that repetition be indefinite.Alternatively or additionally, processor 30 and waveform logic 44 can bearranged to provide a variable delay before starting transmission and/orrepeating transmission. Waveform logic 44 utilizes timer 46 to controlfrequency and other timing aspects (if present), such that the waveformbit pattern transmission to bus 60 is synchronous, at least with respectto the operation of processor 30.

From operation 126, procedure 120 continues with operations 130 and 140that at least partially overlap one another in time—typically beingperformed for the most part concurrently (i.e. in parallel). Inoperation 130, transmission of the waveform is performed under controlof waveform logic 44. In parallel, processor 30 continues to execute adifferent segment or instruction sequence of the routine in operation140 that may correspond to a different process or function as thewaveform is independently transmitted by circuitry 40. In one particularform, the different process includes or is directed to servicing aninterrupt in operation 140 as waveform generation continues in operation130.

Procedure 120 continues with conditional 145 that tests whether tocontinue operation. If the test of conditional 145 is true(affirmative), procedure 120 halts. If the test of conditional 145 isfalse (negative), procedure 120 continues with conditional 150. Itshould be appreciated that the test of conditional 145 can be softwareand/or hardware driven such that it may come from the routine beingexecuted by processor 30, or independent of it.

Conditional 150 tests whether to send a different waveform. If the testof conditional 150 is true (affirmative), procedure 120 loops back tooperation 122 to store the next bit pattern for generation of adifferent waveform, and repeats operations 122, 124, 126, 130 and 140for the new waveform. If the test of conditional 150 is false(negative), procedure 120 proceeds to conditional 160.

Conditional 160 tests whether to terminate waveform transmission. If thetest of conditional 160 is true (affirmative), waveform transmissionterminates in operation 162. In one embodiment, the waveformtransmission termination of operation 150 is performed by waveform logic44 without further input or direction via bus 38 and/or processor 30. Inanother embodiment, processor 30 provides one or more inputs via bus 38that cause waveform logic 44 to terminate transmission. From operation162, procedure 120 returns to conditional 145. If the test ofconditional 160 is false (negative), procedure 120 returns to operation130 and 140. It should appreciated that conditionals 150 and/or 160could be implemented through programming of processor 30; however, suchtests and results may be implemented through hardware input or otherwiseas would be known to those skilled in the art.

Many other embodiments of the present application are envisioned. Forexample, the teachings of the present application can be applied in manydifferent integrated circuit configurations. Another example includesproviding an integrated circuit with a programmable processor, memory,waveform logic operatively coupled to the processor and the memory, andseveral terminals; controlling transmission of the waveform bit patternstored in the memory through one or more of the terminals in accordancewith designated timing; and during this transmission, executing aninstruction sequence for a different process with the processor.

Still a further example includes an integrated circuit with aprogrammable processor, memory operatively coupled to the processor,waveform control circuitry operatively coupled to the processor andmemory, and several terminals. The processor includes means for storinga waveform bit pattern in the memory in accordance with a firstinstruction sequence and executing a second instruction sequence for adifferent process during transmission of a waveform corresponding to thebit pattern under control of the waveform logic. The waveform logicincludes means for controlling transmission of the waveform bit patternstored in the memory through one or more of the terminals in accordancewith desired timing.

Any theory, mechanism of operation, proof, or finding stated herein ismeant to further enhance understanding of the present invention, and isnot intended to limit the present invention in any way to such theory,mechanism of operation, proof, or finding. While the invention has beenillustrated and described in detail in the drawings and foregoingdescription, the same is to be considered as illustrative and notrestrictive in character, it being understood that only selectedembodiments have been shown and described and that all equivalents,changes, and modifications that come within the spirit of the inventionsas defined herein or by the following claims are desired to beprotected.

1. A method, comprising: providing a microcontroller integrated circuitincluding a programmable processor, an embedded memory operativelycoupled to the processor, waveform control circuitry operatively coupledto the processor and the memory, and several terminals each structuredfor coupling to the microcontroller integrated circuit; in accordancewith programming executed by the processor, storing a waveform bitpattern in the memory; with the waveform circuitry, controllingtransmission of the waveform bit pattern stored in the memory throughone or more of the terminals external to the microcontroller integratedcircuit in accordance with desired synchronous timing; and during thetransmission, executing an instruction sequence for a different processwith the processor.
 2. The method of claim 1, wherein the processor, thememory, and the waveform circuitry are coupled to a common bus.
 3. Themethod of claim 1, which includes initiating the transmission with thewaveform control circuitry in response to the processor.
 4. The methodof claim 1, which includes repeating the transmission of the waveformbit in response to the programming executed by the processor.
 5. Themethod of claim 1, wherein the different process includes servicing aninterrupt with the processor.
 6. The method of claim 1, which includesselecting the one or more of the output terminals in accordance with avalue stored in one or more registers by the processor.
 7. The method ofclaim 1, wherein the terminals are provided as general purposeinput/output pins, which includes selectively switching each of theinput/output pins between the memory and one or more other embeddeddevices.
 8. The method of claim 1, which includes controlling input ofinformation into the microcontroller integrated circuit from a circuitdevice external to the microcontroller integrated circuit in response tothe transmission of the waveform bit pattern.
 9. Apparatus, comprising:a microcontroller integrated circuit device including: an embeddedmemory; waveform control circuitry operatively coupled to the memory;several terminals each structured to provide a connection external tothe microcontroller integrated circuit; and a programmable processorresponsive to execution of a first sequence of instructions to store awaveform bit pattern in the embedded memory with a desired transmissiontiming, the waveform circuitry being responsive to the programmableprocessor to control synchronous transmission of the waveform bitpattern stored in the memory through one or more of the terminals inaccordance with the desired timing while the processor executes a secondsequence of instructions to perform a different process with theprocessor.
 10. The apparatus of claim 9, wherein the processor, thememory, and the waveform control circuitry are coupled to a common bus.11. The apparatus of claim 9, wherein the terminals are each a sharedgeneral input/output pin and the microcontroller integrated circuitincludes one or more other embedded devices and one or more registersoperable to selectively switch each of the terminals between the memoryand the one or more other embedded devices.
 12. The apparatus of claim9, wherein the waveform control circuitry includes a timer synchronizedto instruction execution by the processor.
 13. The apparatus of claim 9,wherein the microcontroller integrated circuit includes means forservicing an interrupt during performance of the different process. 14.The apparatus of claim 9, further comprising an external circuit deviceconnected to the one or more terminals of the microcontroller integratedcircuit and the microcontroller integrated circuit, including means forreceiving input data from the circuit device in response to the waveformbit pattern.
 15. A method, comprising: providing a microcontrollerintegrated circuit including a programmable processor, an embeddedmemory operatively coupled to the processor, waveform control circuitryoperatively coupled to the processor and the memory, and severalinput/output pins, the input/output pins each being structured to beselectively switched between the memory and at least one differentembedded device; and executing a first instruction sequence with theprocessor; in response to the executing of the first instructionsequence, the waveform circuitry initiating transmission of a waveformbit pattern stored in the memory through one or more of the input/outputpins and controlling timing of the transmission; and executing a secondinstruction sequence with the processor during the transmission, thetransmission being under control of the waveform circuitry.
 16. Themethod of claim 15, which includes repeating the transmission of thewaveform bit pattern during the executing of the second instructionsequence.
 17. The method of claim 15, wherein the executing of thesecond instruction sequence includes servicing an interrupt with theprocessor.
 18. The method of claim 15, which includes selecting the oneor more of the input/output pins in accordance with a value stored in aregister by the processor.
 19. The method of claim 15, which includescontrolling input of information into the microprocessor from a circuitdevice external to the microcontroller integrated circuit in response tothe transmission of the waveform bit pattern.
 20. Apparatus, comprising:a microcontroller integrated circuit device including: an embeddedmemory; waveform control circuitry operatively coupled to the memory;several input/output pins, the input/output pins being structured toeach be selectively switched between the memory and at least onedifferent embedded device; and a programmable processor including meansfor executing a first sequence of instructions to store a waveform bitpattern in the embedded memory and designate timing for the waveform bitpattern; and wherein the waveform circuitry includes means forcontrolling synchronous transmission of the waveform bit pattern storedin the memory through one or more of the input/output pins in accordancewith the timing while the processor executes a second sequence ofinstructions to perform a different process with the processor.